A Compact Clock Generator for Heterogeneous GALS MPSoCs in 65-nm CMOS TechnologyHOPPNER, Sebastian; EISENREICH, Holger; HENKER, Stephan et al.IEEE transactions on very large scale integration (VLSI) systems. 2013, Vol 21, Num 3, pp 566-570, issn 1063-8210, 5 p.Article

A Wide-Range PLL Using Self-Healing Prescaler/VCO in 65-nm CMOSLEE, I-Ting; TSAI, Yun-Ta; LIU, Shen-Iuan et al.IEEE transactions on very large scale integration (VLSI) systems. 2013, Vol 21, Num 2, pp 250-258, issn 1063-8210, 9 p.Article

Active Filter-Based Hybrid On-Chip DC―DC Converter for Point-of-Load Voltage RegulationKÖSE, Selçuk; TAM, Simon; PINZON, Sally et al.IEEE transactions on very large scale integration (VLSI) systems. 2013, Vol 21, Num 4, pp 680-691, issn 1063-8210, 12 p.Article

Algorithm-Driven Architectural Design Space Exploration of Domain-Specific Medical-Sensor ProcessorsSHOAIB, Mohammed; JHA, Niraj K; VERMA, Naveen et al.IEEE transactions on very large scale integration (VLSI) systems. 2013, Vol 21, Num 10, pp 1849-1862, issn 1063-8210, 14 p.Article

Architecturally Homogeneous Power-Performance Heterogeneous Multicore SystemsCHAKRABORTY, Koushik; ROY, Sanghamitra.IEEE transactions on very large scale integration (VLSI) systems. 2013, Vol 21, Num 4, pp 670-679, issn 1063-8210, 10 p.Article

Architecture and Design Flow for a Highly Efficient Structured ASICHO, Man-Ho; AI, Yan-Qing; CHAU, Thomas Chun-Pong et al.IEEE transactions on very large scale integration (VLSI) systems. 2013, Vol 21, Num 3, pp 424-433, issn 1063-8210, 10 p.Article

BilRC: An Execution Triggered Coarse Grained Reconfigurable ArchitectureATAK, Oguzhan; ATALAR, Abdullah.IEEE transactions on very large scale integration (VLSI) systems. 2013, Vol 21, Num 7, pp 1285-1298, issn 1063-8210, 14 p.Article

Combined Architecture/Algorithm Approach to Fast FPGA RoutingGORT, Marcel; ANDERSON, Jason H.IEEE transactions on very large scale integration (VLSI) systems. 2013, Vol 21, Num 6, pp 1067-1079, issn 1063-8210, 13 p.Article

Concurrent Path Selection Algorithm in Statistical Timing AnalysisJAEYONG CHUNG; ABRAHAM, Jacob A.IEEE transactions on very large scale integration (VLSI) systems. 2013, Vol 21, Num 9, pp 1715-1726, issn 1063-8210, 12 p.Article

Crosstalk- and Process Variations-Aware High-Quality Tests for Small-Delay DefectsKE PENG; YILMAZ, Mahmut; CHAKRABARTY, Krishnendu et al.IEEE transactions on very large scale integration (VLSI) systems. 2013, Vol 21, Num 6, pp 1129-1142, issn 1063-8210, 14 p.Article

Data Allocation Optimization for Hybrid Scratch Pad Memory With SRAM and Nonvolatile MemoryJINGTONG HU; XUE, Chun Jason; ZHUGE, Qingfeng et al.IEEE transactions on very large scale integration (VLSI) systems. 2013, Vol 21, Num 6, pp 1094-1102, issn 1063-8210, 9 p.Article

Design and Analysis of Dual-Mode Digital-Control Step-Up Switched-Capacitor Power Converter With Pulse-Skipping and Numerically Controlled Oscillator-Based Frequency ModulationKWAN, Hing-Kit; NG, David C. W; SO, Victor W. K et al.IEEE transactions on very large scale integration (VLSI) systems. 2013, Vol 21, Num 11, pp 2132-2140, issn 1063-8210, 9 p.Article

Design of a Practical Nanometer-Scale Redundant Via-Aware Standard Cell Library for Improved Redundant Vial Insertion RateKAN, Tsang-Chi; YANG, Shih-Hsien; CHANG, Ting-Feng et al.IEEE transactions on very large scale integration (VLSI) systems. 2013, Vol 21, Num 1, pp 142-147, issn 1063-8210, 6 p.Article

Dual-Level Adaptive Supply Voltage System for Variation ResilienceSHIM, Kyu-Nam; JIANG HU; SILVA-MARTINEZ, Jose et al.IEEE transactions on very large scale integration (VLSI) systems. 2013, Vol 21, Num 6, pp 1041-1052, issn 1063-8210, 12 p.Article

Effects of Using Advanced Cooling Systems on the Overall Power Consumption of ProcessorsWON HO PARK; KEN YANG, Chih-Kong.IEEE transactions on very large scale integration (VLSI) systems. 2013, Vol 21, Num 9, pp 1644-1654, issn 1063-8210, 11 p.Article

Efficient Implementation of Reconfigurable Warped Digital Filters With Variable Low-Pass, High-Pass, Bandpass, and Bandstop ResponsesDARAK, Sumit J; PRASAD, Vinod A; LAI, Edmund M.-K et al.IEEE transactions on very large scale integration (VLSI) systems. 2013, Vol 21, Num 6, pp 1165-1169, issn 1063-8210, 5 p.Article

Efficient VLSI Implementation of 2ⁿ Scaling of Signed Integer in RNS {2ⁿ ― 1, 2ⁿ, 2ⁿ + 1}CHANG, Chip-Hong; JEREMY YUNG SHERN LOW.IEEE transactions on very large scale integration (VLSI) systems. 2013, Vol 21, Num 10, pp 1936-1940, issn 1063-8210, 5 p.Article

Embedded Transition Inversion Coding With Low Switching Activity for Serial LinksCHIU, Ching-Te; HUANG, Wen-Chih; LIN, Chih-Hsing et al.IEEE transactions on very large scale integration (VLSI) systems. 2013, Vol 21, Num 10, pp 1797-1810, issn 1063-8210, 14 p.Article

Embedding Repeaters in Silicon IPs for Cross-IP InterconnectionsWANG, Jinn-Shyan; CHANG, Keng-Jui; YEH, Chingwei et al.IEEE transactions on very large scale integration (VLSI) systems. 2013, Vol 21, Num 3, pp 597-601, issn 1063-8210, 5 p.Article

Enhanced Secure Architecture for Joint Action Test Group SystemsPIERCE, Luke; TRAGOUDAS, Spyros.IEEE transactions on very large scale integration (VLSI) systems. 2013, Vol 21, Num 7, pp 1342-1345, issn 1063-8210, 4 p.Article

Error Rate-Based Wear-Leveling for NAND Flash Memory at Highly Scaled Technology NodesYANGYANG PAN; GUIQIANG DONG; TONG ZHANG et al.IEEE transactions on very large scale integration (VLSI) systems. 2013, Vol 21, Num 7, pp 1350-1354, issn 1063-8210, 5 p.Article

Exploiting Replicated Cache Blocks to Reduce L2 Cache Leakage in CMPsHYUNHEE KIM; JUNG HO AHN; JIHONG KIM et al.IEEE transactions on very large scale integration (VLSI) systems. 2013, Vol 21, Num 10, pp 1863-1877, issn 1063-8210, 15 p.Article

Fast and Effective Placement Refinement for RoutabilityYANHENG ZHANG; CHU, Chris.IEEE transactions on very large scale integration (VLSI) systems. 2013, Vol 21, Num 9, pp 1751-1756, issn 1063-8210, 6 p.Article

Low-Complexity Multiplier for GF(2^m) Based on All-One PolynomialsJIAFENG XIE; KUMAR MEHER, Pramod; JIANJUN HE et al.IEEE transactions on very large scale integration (VLSI) systems. 2013, Vol 21, Num 1, pp 168-173, issn 1063-8210, 6 p.Article

Power-Up Sequence Control for MTCMOS DesignsCHEN, Shi-Hao; LIN, Youn-Long; CHAO, Mango C.-T et al.IEEE transactions on very large scale integration (VLSI) systems. 2013, Vol 21, Num 3, pp 413-423, issn 1063-8210, 11 p.Article